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N25Q032A13ESC40F Datasheet(数据表) 45 Page - Micron Technology

部件型号  N25Q032A13ESC40F
说明  32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
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N25Q032A13ESC40F Datasheet(HTML) 45 Page - Micron Technology

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N25Q032 - 3 V
Protection modes
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
7
Protection modes
There are protocol-related and specific hardware and software protection modes. They are
described below.
7.1
SPI Protocol-related protections
This applies to all three protocols. The environments where non-volatile memory devices
are used can be very noisy. No SPI device can operate correctly in the presence of
excessive noise. To help combat this, the N25Q032 features the following data protection
mechanisms:
Power On Reset and an internal timer (tVTW) can provide protection against
inadvertent changes while the power supply is outside the operating specification.
Program, Erase, and Write Status Register instructions are checked to ensure the
instruction includes a number of clock pulses that is a multiple of a byte before they are
accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events (in Extended SPI protocol mode):
–Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write to Lock Register (WRLR) instruction completion
Program OTP (POTP) instruction completion
Page Program (PP) instruction completion
Dual Input Fast Program (DIFP) instruction completion
Dual Input Extended Fast Program (DIEFP) instruction completion
Quad Input Fast Program (QIFP) instruction completion
Quad Input Extended Fast Program (QIEFP) instruction completion
Subsector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Write Non-Volatile Configuration Register (WRNVCR) instruction completion
This bit is also returned to its reset state after all the analogous events in DIO-SPI and QIO-
SPI protocol modes.




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