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MT47H512M4 数据表(PDF) 81 Page - Micron Technology

部件名 MT47H512M4
功能描述  DDR2 SDRAM MT47H512M4 ??64 Meg x 4 x 8 banks MT47H256M8 ??32 Meg x 8 x 8 banks MT47H128M16 ??16 Meg x 16 x 8 banks
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

MT47H512M4 数据表(HTML) 81 Page - Micron Technology

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CAS Latency (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 36 (page 78). CL is
the delay, in clock cycles, between the registration of a READ command and the availa-
bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may re-
sult.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-
ture allows the READ command to be issued prior to tRCD (MIN) by delaying the inter-
nal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further
detail in Posted CAS Additive Latency (AL) (page 84).
Examples of CL = 3 and CL = 4 are shown in Figure 37; both assume AL = 0. If a READ
command is registered at clock edge n, and the CL is m clocks, the data will be available
nominally coincident with clock edge n + m (this assumes AL = 0).
Figure 37: CL
DO
n + 3
DO
n + 2
DO
n + 1
CK
CK#
Command
DQ
DQS, DQS#
CL = 3 (AL = 0)
READ
T0
T1
T2
Don’t care
Transitioning data
NOP
NOP
NOP
DO
n
T3
T4
T5
NOP
NOP
T6
NOP
DO
n + 3
DO
n + 2
DO
n + 1
CK
CK#
Command
DQ
DQS, DQS#
CL = 4 (AL = 0)
READ
T0
T1
T2
NOP
NOP
NOP
DO
n
T3
T4
T5
NOP
NOP
T6
NOP
Notes:
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
2Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
81
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2006 Micron Technology, Inc. All rights reserved.


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