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N25Q032A13EF840E 数据表(PDF) 36 Page - Micron Technology |
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N25Q032A13EF840E 数据表(HTML) 36 Page - Micron Technology |
36 / 153 page Volatile and Non Volatile Registers N25Q032 - 3 V 36/153 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 6.2.1 Dummy clock cycles NV configuration bits (NVCR bits from 15 to 12) The bits from 15 to 12 of the Non Volatile Configuration register store the default settings for the dummy clock cycles number after the fast read instructions (in all the 3 available protocols). The dummy clock cycles number can be set from 1 up to 15 as described here, according to operating frequency (the higher is the operating frequency, the bigger must be the dummy clock cycle number) to optimize the fast read instructions performance. The default values of these bits allow the memory to be safely used with fast read instructions at the maximum frequency (108 MHz). Please note that if the dummy clock number is not sufficient for the operating frequency, the memory reads wrong data. Table 4. Maximum operative frequency by dummy clock cycles NVCR<5> Reserved x Don’t Care Default value = 1 NVCR<4> Reset/Hold disable 0 disabled Disable Pad Hold/Reset functionality 1 enabled (default) NVCR<3> Quad Input Command 0 enabled Enable command on four input lines 1 disabled (default) NVCR<2> Dual Input Command 0 enabled Enable command on two input lines 1 disabled (default) NVCR<1:0> Reserved xx Don't care Default value = "11" Table 3. Non-Volatile Configuration Register Bit Parameter Value Description Note Maximum allowed frequency (MHz) (1) Dummy Clock FASTREAD DOFR DIOFR QOFR QIOFR 1 54 503943 20 2 95 855956 39 3 105 95 75 70 49 4 108 105 88 83 59 5 108 108 94 94 69 6 108 108 105 105 78 7 108 108 108 108 86 8 108 108 108 108 95 9 108 108 108 108 105 10 108 108 108 108 108 1. All the values are guaranteed by characterization and not 100% tested in production |
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