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N25Q032A13EF840E 数据表(PDF) 72 Page - Micron Technology |
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N25Q032A13EF840E 数据表(HTML) 72 Page - Micron Technology |
72 / 153 page Instructions N25Q032 - 3 V 72/153 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the OTP memory array become read-only in a permanent way. Any Program OTP (POTP) instruction issued while an Erase or Program is in progress is rejected without having any effect on the cycle that is in progress. A Program OTP cycle cannot be paused by a Program/Erase Suspend (PES) instruction. Figure 26. Program OTP instruction sequence C DQ0 S 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 C DQ0 S 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 Instruction 24-bit address 0 765432 0 1 Data byte 1 39 51 765432 0 1 Data byte 2 765432 0 1 Data byte 3 Data byte n 765432 0 1 MSB MSB MSB MSB MSB |
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类似说明 - N25Q032A13EF840E |
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