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N25Q032A13EF840E 数据表(PDF) 44 Page - Micron Technology |
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N25Q032A13EF840E 数据表(HTML) 44 Page - Micron Technology |
44 / 153 page Volatile and Non Volatile Registers N25Q032 - 3 V 44/153 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. The Program Status bit is related to the following program operations in the DIO-SPI and QIO-SPI protocols: Dual and Quad Command Page program and OTP program. Once the bit is set High, it can only be reset Low (FSR<4>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new Program command is issued, otherwise the new command will appear to fail. 6.5.5 VPP Status bit The bit 3 of the Flag Status Register represents the VPP Status bit. It indicates an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is sampled at the beginning of a Program or Erase operation. If VPP becomes invalid during an operation, that is the voltage on VPP pin is below the VPPH Voltage (9V), the VPP Status bit goes High (FSR<3>=1) and indeterminate results can occur. Once set High, the VPP Status bit can only be reset Low (FSR<3>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new Program or Erase command is issued; otherwise, the new command will appear to fail. 6.5.6 Program Suspend Status bit The bit 2 of the Flag Status register represents the Program Suspend Status bit. It indicates that a Program operation has been suspended or is going to be suspended. The bit is set (FSR<2>=1) within the Program Suspend Latency time; that is, as soon as the Program/Erase Suspend command (PES) has been issued. Therefore the device may still complete the operation before entering the Suspend Mode. The Program Suspend Status should be considered valid when the P/E Controller bit is high (FSR<7>=1). When a Program/Erase Resume command (PER) is issued the Program Suspend Status bit returns Low (FSR<2>=0) 6.5.7 Protection Status bit The bit 1 of the Flag Status Register represents the Protection Status bit. It indicates that an Erase or Program operation has tried to modify the contents of a protected array sector, or that a modify operation has tried to access to a locked OTP space. The Protection Status bit is related to all possible protection violations as follows: n The sector is protected by Software Protection Mode 1 (SPM1) Lock registers, n The sector is protected by Software Protection Mode 2 (SPM2) Block Protect Bits (standard SPI Status Register), n An attempt to program OTP when locked, n A Write Status Register command (WRSR) on STD SPI Status Register when locked by the SRWD bit in conjunction with the Write Protect (W/VPP) signal (Hardware Protection Mode). Once set High, the Protection Status bit can only be reset Low (FSR<1>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. |
类似零件编号 - N25Q032A13EF840E |
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类似说明 - N25Q032A13EF840E |
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