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SI5326C-C-GM 数据表(PDF) 10 Page - Silicon Laboratories |
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SI5326C-C-GM 数据表(HTML) 10 Page - Silicon Laboratories |
10 / 72 page Si5326 10 Rev. 1.0 SPI Specifications Duty Cycle, SCLK tDC SCLK = 10 MHz 40 — 60 % Cycle Time, SCLK tc 100 — — ns Rise Time, SCLK tr 20–80% — — 25 ns Fall Time, SCLK tf 20–80% — — 25 ns Low Time, SCLK tlsc 20–20% 30 — — ns High Time, SCLK thsc 80–80% 30 — — ns Delay Time, SCLK Fall to SDO Active td1 —— 25 ns Delay Time, SCLK Fall to SDO Transition td2 —— 25 ns Delay Time, SS Rise to SDO Tri-state td3 —— 25 ns Setup Time, SS to SCLK Fall tsu1 25 — — ns Hold Time, SS to SCLK Rise th1 20 — — ns Setup Time, SDI to SCLK Rise tsu2 25 — — ns Hold Time, SDI to SCLK Rise th2 20 — — ns Delay Time between Slave Selects tcs 25 — — ns Table 3. Microprocessor Control (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit |
类似零件编号 - SI5326C-C-GM |
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类似说明 - SI5326C-C-GM |
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