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BU4313 数据表(PDF) 11 Page - Rohm

部件名 BU4313
功能描述  Low Voltage Free Delay Time Setting CMOS Voltage Detector IC Series
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制造商  ROHM [Rohm]
网页  http://www.rohm.com
标志 ROHM - Rohm

BU4313 数据表(HTML) 11 Page - Rohm

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Datasheet
11/13
BU42xx series
BU43xx series
TSZ02201-0R7R0G300050-1-2
© 2013 ROHM Co., Ltd. All rights reserved.
22.May.2013 Rev.006
www.rohm.com
TSZ22111
15
001
Circuit Applications
1) Examples of common power supply detection reset circuits
Application examples of BU42xx series
(Open Drain output type) and BU43xx series
(CMOS output type) are shown below.
CASE1: Power supply of microcontroller (VDD2) differs
from the power supply of the reset detection (VDD1).
Use an open drain output Type (BU42xx series) device
with a load resistance RL as shown Fig.18.
CASE2: Power supply of microcontroller (VDD1) is the
same as the power supply of the reset detection (VDD1).
Use a CMOS output type (BU43xx series) device or an
open drain output type (BU42xx series) device with a pull
up resistor between the output and VDD1.
When a capacitance CL for noise filtering is connected to
VouT pin (the reset signal input terminal of the
microcontroller), please take into account the waveform
of the rise and fall time of the output voltage (VouT).
2) The following is an example of a circuit application in which an OR connection between two types of detection voltage
resets the microcontroller.
To reset the microcontroller when many independent power supplies are used in the system, OR connect an open drain
output type (BU42xx series) to the microcontroller’s input with pull-up resistor to the supply voltage of the microcontroller
(VDD3) as shown in Fig. 20. By pulling-up to VDD3, output “High” voltage of micro-controller power supply is possible.
VDD1
BU43xx
CIN
GND
CT
RST
CL
(Capacitor for
noise filtering)
Micro
controller
Fig.19 CMOS Output type
VDD1
BU42xx
VDD2
GND
RST
CL
(Capacitor for
noise filtering)
CT
RL
CIN
Micro
controller
Fig.18 Open Drain Output type
VDD1
VDD3
GND
RST
microcontroller
CT
RL
VDD2
CT
BU42xx
NO.1
BU42xx
NO.2
Fig.20


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