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FM24C08U/09U Rev. A.3

Write Operations

BYTE WRITE

For a write operation, a second address field is required which is a

word address that is comprised of eight bits and provides access to

any one of the 256 bytes in the selected page of memory. Upon

receipt of the byte address, the FM24C08U/09U responds with an

acknowledge and waits for the next eight bits of data, again,

responding with an acknowledge. The master then terminates the

transfer by generating a stop condition at which time the FM24C08U/

09U begins the internal write cycle to the nonvolatile memory. While

the internal write cycle is in progress, the FM24C08U/09U inputs

are disabled, and the device will not respond to any requests from

the master for the duration of t

acknowledge, and data transfer sequence.

PAGE WRITE

To minimize write cycle time, FM24C08U/09U offer Page Write

feature, by which, up to a maximum of 16 contiguous byte

locations can be programmed all at once (instead of 16 individual

byte writes). To facilitate this feature, the memory array is orga-

nized in terms of “Pages.” A Page consists of 16 contiguous byte

locations starting at every 16-Byte address boundary (for ex-

ample, starting at array address 0x00, 0x10, 0x20 etc.). Page

Write operation limits access to byte locations within a page. In

other words a single Page Write operation will not cross over to

locations on another page but will “roll over” to the beginning of the

page whenever end of Page is reached and additional locations

are continued to be accessed. A Page Write operation can be

initiated to begin at any location within a page (starting address of

the Page Write operation need not be the starting address of a

Page).

S

T

O

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Bus Activity:

Master

SDA Line

Bus Activity:

EEPROM

DATA n + 15

DATA n + 1

DATA n

WORD ADDRESS (n)

A

C

K

S

T

A

R

T

SLAVE

ADDRESS

A

C

K

A

C

K

A

C

K

A

C

K

S

T

O

P

A

C

K

DATA

A

C

K

A

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K

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A

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WORD

ADDRESS

SLAVE

ADDRESS

Bus Activity:

Master

SDA Line

Bus Activity:

EEPROM

Page Write is initiated in the same manner as the Byte Write

operation; but instead of terminating the cycle after transmitting

the first data byte, the master can further transmit up to 15 more

bytes. After the receipt of each byte, FM24C08U/09U will respond

with an acknowledge pulse, increment the internal address counter

to the next address, and is ready to accept the next data. If the

master should transmit more than sixteen bytes prior to generat-

ing the STOP condition, the address counter will “roll over” and

previously written data will be overwritten. As with the Byte Write

operation, all inputs are disabled until completion of the internal

write cycle. Refer to

Figure 5 for the address, acknowledge, and

data transfer sequence.

Acknowledge Polling

Once the stop condition is issued to indicate the end of the host’s

write operation, the FM24C08U/09U initiates the internal write

cycle. ACK polling can be initiated immediately. This involves

issuing the start condition followed by the slave address for a write

operation. If the FM24C08U/09U is still busy with the write

operation, no ACK will be returned. If the FM24C08U/09U has

completed the write operation, an ACK will be returned and the

host can then proceed with the next read or write operation.

Write Protection (FM24C09U Only)

Programming of the upper half (upper 4Kbit) of the memory will not

The FM24C09U will respond to slave and byte addresses; but if

the memory accessed is write protected by the WP pin, the

FM24C09U will not generate an acknowledge after the first byte

of data has been received. Thus the program cycle will not be

started when the stop condition is asserted.

Byte Write (Figure 4)

Page Write (Figure 5)