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EPM240G 数据表(PDF) 53 Page - Altera Corporation |
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EPM240G 数据表(HTML) 53 Page - Altera Corporation |
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53 / 88 page  Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices 4–3 Hot Socketing Feature Implementation in MAX II Devices © October 2008 Altera Corporation MAX II Device Handbook 1 Make sure that the V CCINT is within the recommended operating range even though SRAM download has completed. Each I/O and clock pin has the circuitry shown in Figure 4–1. The POR circuit monitors V CCINT and VCCIO voltage levels and keeps I/O pins tri-stated until the device has completed its flash memory configuration of the SRAM logic. The weak pull-up resistor (R) from the I/O pin to V CCIO is enabled during download to keep the I/O pins from floating. The 3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3 V before V CCIO and/or VCCINT are powered, and it prevents the I/O pins from driving out when the device is not fully powered or operational. The hot socket circuit prevents I/O pins from internally powering V CCIO and VCCINT when driven by external signals before the device is powered. f For information about 5.0-V tolerance, refer to the Using MAX II Devices in Multi- Voltage Systems chapter in the MAX II Device Handbook. Figure 4–2 shows a transistor-level cross section of the MAX II device I/O buffers. This design ensures that the output buffers do not drive when V CCIO is powered before V CCINT or if the I/O pad voltage is higher than VCCIO. This also applies for sudden voltage spikes during hot insertion. The V PAD leakage current charges the 3.3-V tolerant circuit capacitance. Figure 4–1. Hot Socketing Circuit Block Diagram for MAX II Devices Output Enable V CCIO Hot Socket Voltage Tolerance Control Power On Reset Monitor Weak Pull-Up Resistor PAD Input Buffer to Logic Array |
类似零件编号 - EPM240G |
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类似说明 - EPM240G |
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