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EPM240 数据表(PDF) 74 Page - Altera Corporation |
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EPM240 数据表(HTML) 74 Page - Altera Corporation |
74 / 88 page 5–16 Chapter 5: DC and Switching Characteristics Timing Model and Specifications MAX II Device Handbook © August 2009 Altera Corporation Figure 5–3 through Figure 5–5 show the read, program, and erase waveforms for UFM block timing parameters shown in Table 5–21. t OE Delay from data register clock to data register output 180 — 180 — 180 — 180 — 180 — 180 — ns t RA Maximum read access time — 65 — 65 — 65 — 65 — 65 — 65 ns t OSC S Maximum delay between the OSC_ENA rising edge to the erase/program signal rising edge 250 — 250 — 250 — 250 — 250 — 250 — ns t OSC H Minimum delay allowed from the erase/program signal going low to OSC_ENA signal going low 250 — 250 — 250 — 250 — 250 — 250 — ns Table 5–21. UFM Block Internal Timing Microparameters (Part 3 of 3) Symbol Parameter MAX II / MAX IIG MAX IIZ Unit –3 Speed Grade –4 Speed Grade –5 Speed Grade –6 Speed Grade –7 Speed Grade –8 Speed Grade Min Max Min Max Min Max Min Max Min Max Min Max Figure 5–3. UFM Read Waveforms t DCO t DCLK t DSS t DSH t ADH t ADS t ASU t ACLK t AH ARShft ARClk ARDin DRShft DRClk DRDin DRDout Program Erase Busy 16 Data Bits 9 Address Bits OSC_ENA |
类似零件编号 - EPM240 |
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类似说明 - EPM240 |
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