ADC0831-N, ADC0832-N, ADC0834-N, ADC0838-N

SNAS531B – AUGUST 1999 – REVISED MARCH 2013

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AC Characteristics

Tested

Design

Limit

Parameter

Conditions

Units

Min

10

kHz

Max

400

kHz

Not including MUX Addressing Time

8

Min

40

%

Max

60

%

250

ns

to CLK Rising Edge

90

ns

Edge

Data MSB First

650

1500

ns

Data LSB First

250

600

ns

125

250

ns

Test Circuits and Waveforms)

and SARS Hi–Z

500

ns

5

pF

5

pF

(1)

Typicals are at 25°C and represent most likely parametric norm.

(2)

Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).

(3)

Ensured but not 100% production tested. These limits are not used to calculate outgoing quality levels.

(4)

A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty

cycle outside of these limits, the minimum, time the clock is high or the minimum time the clock is low must be at least 1

μs. The

maximum time the clock can be high is 60

μs. The clock can be stopped when low so long as the analog input voltage remains stable.

(5)

Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see

ADC0838-N Functional Block Diagram) to allow for comparator response time.

6

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