© 2002 Fairchild Semiconductor Corporation

DS500730

www.fairchildsemi.com

February 2002

Revised February 2002

FIN1002

LVDS 1-Bit High Speed Differential Receiver

General Description

This single receiver is designed for high speed intercon-

nects utilizing Low Voltage Differential Signaling (LVDS)

technology. The receiver translates LVDS levels, with a typ-

ical differential input threshold of 100 mV, to LVTTL signal

levels. LVDS provides low EMI at ultra low power dissipa-

tion even at high frequencies. This device is ideal for high

speed transfer of clock or data.

The FIN1002 can be paired with its companion driver, the

FIN1001, or with any other LVDS driver.

Features

s Greater than 400Mbs data rate

s 3.3V power supply operation

s 0.4ns maximum pulse skew

s 2.5ns maximum propagation delay

s Bus pin ESD (HBM) protection exceeds 10kV

s Power-Off over voltage tolerant input and output

s Fail safe protection for open-circuit and non-driven,

shorted or terminated conditions

s Meets or exceeds the TIA/EIA-644 LVDS standard

s 5-Lead SOT23 package saves space

Ordering Code:

Pin Descriptions

Function Table

H

= HIGH Logic Level

L

= LOW Logic Level

Fail Safe

= Open, Shorted, Terminated

Connection Diagram

Pin Assignment for SOT package

Top View

Order Number

Package Number

Package Description

FIN1002M5

MA05B

5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel]

FIN1002M5X

MA05B

5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel]

Pin Name

Description

LVTTL Data Output

Non-inverting Driver Input

Inverting Driver Input

Power Supply

GND

Ground

NC

No Connect

Input

Outputs

LH

L

HL

H

Fail Safe Condition

H