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5SGXEB6R2F40C3N 数据表(PDF) 64 Page - Altera Corporation |
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5SGXEB6R2F40C3N 数据表(HTML) 64 Page - Altera Corporation |
64 / 70 page 2–36 Chapter 2: DC and Switching Characteristics for Stratix V Devices Glossary Stratix V Device Handbook February 2012 Altera Corporation Volume 1: Overview and Datasheet J J High-speed I/O block—Deserialization factor (width of parallel data bus). JTAG Timing Specifications JTAG Timing Specifications: K L M N O —— P PLL Specifications Diagram of PLL Specifications (1) Note: (1) Core Clock can only be fed by dedicated clock input pins or PLL outputs. Q —— RRL Receiver differential input discrete resistor (external to the Stratix V device). Table 2–41. Glossary (Part 2 of 4) Letter Subject Definitions TDO TCK tJPZX t JPCO tJPH t JPXZ tJCP tJPSU t JCL tJCH TDI TMS Core Clock External Feedback Reconfigurable in User Mode Key CLK N PFD Switchover Delta Sigma Modulator VCO CP LF CLKOUT Pins GCLK RCLK fINPFD fIN fVCO fOUT fOUT_EXT Counters C0..C17 4 |
类似零件编号 - 5SGXEB6R2F40C3N |
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类似说明 - 5SGXEB6R2F40C3N |
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