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ADP162ACBZ-2.3-R7 数据表(PDF) 4 Page - Analog Devices

部件名 ADP162ACBZ-2.3-R7
功能描述  Ultralow Quiescent Current, 150 mA, CMOS Linear Regulators
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP162ACBZ-2.3-R7 数据表(HTML) 4 Page - Analog Devices

  ADP162ACBZ-2.3-R7 Datasheet HTML 1Page - Analog Devices ADP162ACBZ-2.3-R7 Datasheet HTML 2Page - Analog Devices ADP162ACBZ-2.3-R7 Datasheet HTML 3Page - Analog Devices ADP162ACBZ-2.3-R7 Datasheet HTML 4Page - Analog Devices ADP162ACBZ-2.3-R7 Datasheet HTML 5Page - Analog Devices ADP162ACBZ-2.3-R7 Datasheet HTML 6Page - Analog Devices ADP162ACBZ-2.3-R7 Datasheet HTML 7Page - Analog Devices ADP162ACBZ-2.3-R7 Datasheet HTML 8Page - Analog Devices ADP162ACBZ-2.3-R7 Datasheet HTML 9Page - Analog Devices Next Button
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ADP160/ADP161/ADP162/ADP163
Data Sheet
Rev. G | Page 4 of 24
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
UNDERVOLTAGE LOCKOUT
UVLO
Input Voltage Rising
UVLO
RISE
2.19
V
Input Voltage Falling
UVLO
FALL
1.60
V
Hysteresis
UVLO
HYS
100
mV
OUTPUT NOISE
OUT
NOISE
10 Hz to 100 kHz, V
IN = 5 V, VOUT = 3.3 V
105
µV
rms
10 Hz to 100 kHz, V
IN = 5 V, VOUT = 2.5 V
100
µV
rms
10 Hz to 100 kHz, V
IN = 5 V, VOUT = 1.2 V
80
µV
rms
POWER SUPPLY REJECTION RATIO
PSRR
100 Hz, V
IN = 5 V, VOUT = 3.3 V
60
dB
100 Hz, V
IN = 5 V, VOUT = 2.5 V
65
dB
100 Hz, V
IN = 5 V, VOUT = 1.2 V
72
dB
1 kHz, V
IN = 5 V, VOUT = 3.3 V
50
dB
1 kHz, V
IN = 5 V, VOUT = 2.5 V
50
dB
1 kHz, V
IN = 5 V, VOUT = 1.2 V
62
dB
1 Accuracy when VOUT is connected directly to ADJ. When the VOUT voltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on the
tolerances of resistors used.
2 Based on an end-point calculation using 0 μA and 150 mA loads.
3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.2 V.
4 Start-up time is defined as the time between the rising edge of EN to V
OUT being at 90% of its nominal value.
5 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE1
C
MIN
T
A = −40°C to +125°C
0.7
µF
CAPACITOR ESR
R
ESR
T
A = −40°C to +125°C
0.001
0.2
Ω
1 The minimum input and output capacitance should be greater than 0.7 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
however, Y5V and Z5U capacitors are not recommended for use with any LDO.


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