ADF4116BRU-REEL datasheet(5/28 Pages) AD

部件名	ADF4116BRU-REEL

功能描述	RF PLL Frequency Synthesizers

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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ADF4116/ADF4117/ADF4118

Rev. D | Page 5 of 28

TIMING CHARACTERISTICS

AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP < 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.

Guaranteed by design, but not production tested.

Table 2.

Parameter

Limit at TMIN to TMAX (B, Y Version)

Unit

Test Conditions/Comments

t1

10

ns min

DATA to CLK setup time

t2

10

ns min

DATA to CLK hold time

t3

25

ns min

CLK high duration

t4

25

ns min

CLK low duration

t5

10

ns min

CLK to LE setup time

t6

20

ns min

LE pulse width

CLK

DATA

LE

DB20 (MSB)

DB19

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t5

t2

t4

t6

t1

t3

Figure 2. Timing Diagram

类似零件编号 - ADF4116BRU-REEL

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Analog Devices	ADF4116BRU	226Kb / 20P	RF PLL Frequency Synthesizers REV. 0
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制造商	部件名	数据表	功能描述
Analog Devices	ADF4111	428Kb / 28P	RF PLL Frequency Synthesizers Rev. F
	ADF4116	486Kb / 28P	RF PLL Frequency Synthesizers REV. D
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	ADF4116	226Kb / 20P	RF PLL Frequency Synthesizers REV. 0
	ADF4110	428Kb / 28P	RF PLL Frequency Synthesizers Rev. F
	ADF4113	428Kb / 28P	RF PLL Frequency Synthesizers Rev. F
	ADF4118	486Kb / 28P	RF PLL Frequency Synthesizers REV. D
	EVAL-ADF4113EBZ1	428Kb / 28P	RF PLL Frequency Synthesizers Rev. F
	ADF4110	428Kb / 28P	RF PLL Frequency Synthesizers Rev. F
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ADF4116BRU-REEL 数据表(PDF) 5 Page - Analog Devices

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