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TC4467 数据表(PDF) 9 Page - Microchip Technology |
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TC4467 数据表(HTML) 9 Page - Microchip Technology |
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9 / 22 page  2001-2012 Microchip Technology Inc. DS21425C-page 9 TC4467/TC4468/TC4469 4.0 DETAILED DESCRIPTION 4.1 Supply Bypassing Large currents are required to charge and discharge large capacitive loads quickly. For example, charging a 1000 pF load to 18 V in 25 nsec requires 0.72 A from the device's power supply. To ensure low supply impedance over a wide frequency range, a 1 µF film capacitor in parallel with one or two low-inductance, 0.1 µF ceramic disk capacitors with short lead lengths (<0.5 in.) normally provide adequate bypassing. 4.2 Grounding The TC4467 and TC4469 contain inverting drivers. Potential drops developed in common ground impedances from input to output will appear as negative feedback and degrade switching speed characteristics. Instead, individual ground returns for input and output circuits, or a ground plane, should be used. 4.3 Input Stage The input voltage level changes the no-load or quiescent supply current. The N-channel MOSFET input stage transistor drives a 2.5 mA current source load. With logic “0” outputs, maximum quiescent supply current is 4 mA. Logic “1” output level signals reduce quiescent current to 1.4 mA, maximum. Unused driver inputs must be connected to VDD or VSS. Minimum power dissipation occurs for logic “1” outputs. The drivers are designed with 50 mV of hysteresis, which provides clean transitions and minimizes output stage current spiking when changing states. Input volt- age thresholds are approximately 1.5 V, making any voltage greater than 1.5 V, up to VDD, a logic “1” input. Input current is less than 1 µA over this range. 4.4 Power Dissipation The supply current versus frequency and supply current versus capacitive load characteristic curves will aid in determining power dissipation calculations. Microchip Technology's CMOS drivers have greatly reduced quiescent DC power consumption. Input signal duty cycle, power supply voltage and load type influence package power dissipation. Given power dissipation and package thermal resistance, the maxi- mum ambient operating temperature is easily calculated. The 14-pin plastic package junction-to- ambient thermal resistance is 83.3°C/W. At +70°C, the package is rated at 800 mW maximum dissipation. Maximum allowable chip temperature is +150°C. Three components make up total package power dissipation: 1. Load-caused dissipation (PL). 2. Quiescent power (PQ). 3. Transition power (PT). A capacitive-load-caused dissipation (driving MOSFET gates), is a direct function of frequency, capacitive load and supply voltage. The power dissipation is: EQUATION A resistive-load-caused dissipation for ground- referenced loads is a function of duty cycle, load current and load voltage. The power dissipation is: EQUATION P L fCV S 2 = V S Supply Voltage = C Capacitive Load = f Switching Frequency = P L DV S V L – I L = I L Load Current = DDuty Cycle = V S Supply Voltage = V L Load Voltage = |
类似零件编号 - TC4467_13 |
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类似说明 - TC4467_13 |
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