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LCMXO2-256ZE-3MG132C 数据表(PDF) 22 Page - Lattice Semiconductor |
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LCMXO2-256ZE-3MG132C 数据表(HTML) 22 Page - Lattice Semiconductor |
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22 / 106 page  2-18 Architecture MachXO2 Family Data Sheet Figure 2-15. MachXO2 Output Register Block Diagram (PIO on the Right Edges) Tri-state Register Block The tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then feeds the output. The tri-state register blocks on the right edge contain an additional register for DDR memory operation. In DDR memory mode, the register TS input is fed into another register that is clocked using the DQSW90 signal. The out- put of this register is used as a tri-state control. Input Gearbox Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2-9 shows the gearbox signals. Table 2-9. Input Gearbox Signal List Name I/O Type Description D Input High-speed data input after programmable delay in PIO A input register block ALIGNWD Input Data alignment signal from device core SCLK Input Slow-speed system clock ECLK[1:0] Input High-speed edge clock RST Input Reset Q[7:0] Output Low-speed data to device core: Video RX(1:7): Q[6:0] GDDRX4(1:8): Q[7:0] GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7 GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3 D Q D1 D Q Q1 D/L Q Q0 D0 DQSW90 Q SCLK D Q TQ D/L Q T0 TD Output Register Block Tristate Register Block |
类似零件编号 - LCMXO2-256ZE-3MG132C |
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类似说明 - LCMXO2-256ZE-3MG132C |
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