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LCMXO2-256ZE-3TG100C 数据表(PDF) 17 Page - Lattice Semiconductor |
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LCMXO2-256ZE-3TG100C 数据表(HTML) 17 Page - Lattice Semiconductor |
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17 / 106 page  2-13 Architecture MachXO2 Family Data Sheet For further information on the sysMEM EBR block, please refer to TN1201, Memory Usage Guide for MachXO2 Devices. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-10. The GSR input to the EBR is always asynchronous. Figure 2-10. EBR Asynchronous Reset (Including GSR) Timing Diagram If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device wake up must occur before the release of the device I/Os becoming active. These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR sig- nal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-10. The reset timing rules apply to the RPReset input versus the RE input and the RST input versus the WE and RE inputs. Both RST and RPReset are always asynchronous EBR inputs. For more details refer to TN1201, Memory Usage Guide for MachXO2 Devices. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. Programmable I/O Cells (PIC) The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respec- tive sysIO buffers and pads. On the MachXO2 devices, the PIO cells are assembled into groups of four PIO cells called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device. On all the MachXO2 devices, two adjacent PIOs can be combined to provide a complementary output driver pair. The MachXO2-640U, MachXO2-1200/U and higher density devices contain enhanced I/O capability. All PIO pairs on these larger devices can implement differential receivers. Half of the PIO pairs on the top edge of these devices can be configured as true LVDS transmit pairs. The PIO pairs on the bottom edge of these higher density devices have on-chip differential termination and also provide PCI support. Reset Clock Clock Enable |
类似零件编号 - LCMXO2-256ZE-3TG100C |
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类似说明 - LCMXO2-256ZE-3TG100C |
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