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LCMXO2-256ZE-1TG100C 数据表(PDF) 76 Page - Lattice Semiconductor |
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LCMXO2-256ZE-1TG100C 数据表(HTML) 76 Page - Lattice Semiconductor |
76 / 106 page 3-37 DC and Switching Characteristics MachXO2 Family Data Sheet Switching Test Conditions Figure 3-13 shows the output test load used for AC testing. The specific values for resistance, capacitance, volt- age, and other test conditions are shown in Table 3-5. Figure 3-13. Output Test Load, LVTTL and LVCMOS Standards Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces Note: Output test conditions for all other interfaces are determined by the respective standards. Test Condition R1 CL Timing Ref. VT LVTTL and LVCMOS settings (L -> H, H -> L) 0pF LVTTL, LVCMOS 3.3 = 1.5V — LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 1.5 = VCCIO/2 — LVCMOS 1.2 = VCCIO/2 — LVTTL and LVCMOS 3.3 (Z -> H) 188 0pF 1.5 VOL LVTTL and LVCMOS 3.3 (Z -> L) 1.5 VOH Other LVCMOS (Z -> H) VCCIO/2 VOL Other LVCMOS (Z -> L) VCCIO/2 VOH LVTTL + LVCMOS (H -> Z) VOH - 0.15 VOL LVTTL + LVCMOS (L -> Z) VOL - 0.15 VOH DUT VT R1 CL Test Poi nt |
类似零件编号 - LCMXO2-256ZE-1TG100C |
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类似说明 - LCMXO2-256ZE-1TG100C |
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