LCMXO2-256ZE-3UMG64C datasheet(73/106 Pages) LATTICE

部件名	LCMXO2-256ZE-3UMG64C

功能描述	MachXO2??Family Data Sheet

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制造商	LATTICE [Lattice Semiconductor]

网页	http://www.latticesemi.com

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3-34

DC and Switching Characteristics

MachXO2 Family Data Sheet

Flash Download Time

1, 2

JTAG Port Timing Specifications

Symbol

Parameter

Device

Typ.

Units

tREFRESH

POR to Device I/O Active

LCMXO2-256

0.6

ms

LCMXO2-640

1.0

ms

LCMXO2-640U

1.9

ms

LCMXO2-1200

1.9

ms

LCMXO2-1200U

1.4

ms

LCMXO2-2000

1.4

ms

LCMXO2-2000U

2.4

ms

LCMXO2-4000

2.4

ms

LCMXO2-7000

3.8

ms

1. Assumes sysMEM EBR initialized to an all zero pattern if they are used.

2. The Flash download time is measured starting from the maximum voltage of POR trip point.

Symbol

Parameter

Min.

Max.

Units

fMAX

TCK clock frequency

—

25

MHz

tBTCPH

TCK [BSCAN] clock pulse width high

20

—

ns

tBTCPL

TCK [BSCAN] clock pulse width low

20

—

ns

tBTS

TCK [BSCAN] setup time

10

—

ns

tBTH

TCK [BSCAN] hold time

8

—

ns

tBTCO

TAP controller falling edge of clock to valid output

—

10

ns

tBTCODIS

TAP controller falling edge of clock to valid disable

—

10

ns

tBTCOEN

TAP controller falling edge of clock to valid enable

—

10

ns

tBTCRS

BSCAN test capture register setup time

8

—

ns

tBTCRH

BSCAN test capture register hold time

20

—

ns

tBUTCO

BSCAN test update register, falling edge of clock to valid output

—

25

ns

tBTUODIS

BSCAN test update register, falling edge of clock to valid disable

—

25

ns

tBTUPOEN

BSCAN test update register, falling edge of clock to valid enable

—

25

ns

类似零件编号 - LCMXO2-256ZE-3UMG64C

制造商	部件名	数据表	功能描述
Lattice Semiconductor	LCMXO2-256ZE-3UMG64C	5Mb / 122P	MachXO2 Family Data Sheet 2010-2022

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