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LCMXO2-256ZE-3SG32C 数据表(PDF) 25 Page - Lattice Semiconductor |
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LCMXO2-256ZE-3SG32C 数据表(HTML) 25 Page - Lattice Semiconductor |
25 / 106 page 2-21 Architecture MachXO2 Family Data Sheet Figure 2-17. Output Gearbox More information on the output gearbox is available in TN1203, Implementing High-Speed Interfaces with MachXO2 Devices. DDR Memory Support Certain PICs on the right edge of MachXO2-640U, MachXO2-1200/U and larger devices, have additional circuitry to allow the implementation of DDR memory interfaces. There are two groups of 14 or 12 PIOs each on the right edge with additional circuitry to implement DDR memory interfaces. This capability allows the implementation of up to 16-bit wide memory interfaces. One PIO from each group contains a control element, the DQS Read/Write D4 D0 D3 D1 S1 T1 S0 QC ODDRx2_A ODDRx2_C ODDRx2_C ECLK0/1 Q45 Q67 S4 S6 D Q D Q T4 T6 D6 D Q D Q CE D Q CE 0 1 0 1 Q01 Q23 S0 S2 T0 T2 Q32 Q10 S5 S3 D Q T5 T3 CE 0 1 D Q Q76 Q54 S7 D Q T7 D Q D Q D Q CE 0 1 S2 S4 GND S7 S6 S5 S3 D2 D7 D5 SCLK 0 1 0 1 0 1 1 0 1 Q34 Q56 Q67 GND Q45 S1 Q12 SEL /0 UPDATE Q23 Q/QA D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q 0 1 0 1 0 1 0 1 0 1 0 CE CE D Q CE D Q CE 0 1 0 1 CDN |
类似零件编号 - LCMXO2-256ZE-3SG32C |
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类似说明 - LCMXO2-256ZE-3SG32C |
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