October 1997

FDC6302P

Digital FET, Dual P-Channel

General Description

Features

Symbol

Parameter

FDC6302P

Units

V

DSS

Drain-Source Voltage

-25

V

V

GSS

Gate-Source Voltage

-8

V

I

D

Drain Current

- Continuous

-0.12

A

- Pulsed

-0.5

P

D

Maximum Power Dissipation

(Note 1a)

0.9

W

(Note 1b)

0.7

T

Operating and Storage Temperature Range

-55 to 150

°C

ESD

Electrostatic Discharge Rating MIL-STD-883D

Human Body Model (100pf / 1500 Ohm)

6.0

kV

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient

(Note 1a)

140

°C/W

Thermal Resistance, Junction-to-Case

(Note 1)

60

°C/W

FDC6302P Rev.C

-25 V, -0.12 A continuous, -0.5 A Peak.

R

R

Very low level gate drive requirements allowing direct

operation in 3V circuits. V

Gate-Source Zener for ESD ruggedness.

>6kV Human Body Model

Replace multiple PNP digital transistors (IMHxA series) with

one DMOS FET.

These Dual P-Channel logic level enhancement mode field effect

transistors are produced using Fairchild's proprietary, high cell

density, DMOS technology. This very high density process is

especially tailored to minimize on-state resistance. This device

has been designed especially for low voltage applications as a

replacement for digital transistors in load switchimg applications.

Since bias resistors are not required this one P-Channel FET

can replace several digital transistors with different bias resistors

like the IMBxA series.

SOT-23

SuperSOT

SOIC-16

SO-8

SOT-223

SuperSOT

5

6

3

2

1

4

© 1997 Fairchild Semiconductor Corporation