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DM74S374N 数据表(PDF) 2 Page - Fairchild Semiconductor |
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DM74S374N 数据表(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 Truth Tables DM74S373 H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don’t Care Z = High Impedance State ↑ = Transition from LOW-to-HIGH level, Q0 = The level of the output before steady-state input conditions were established. DM74S374 Logic Diagrams 74S373 Transparent Latches 74S374 Positive-Edge-Triggered Flip-Flops Output Enable D Output Control G L HHH LH L L LL X Q0 HX X Z Output Clock D Output Control L ↑ HH L ↑ LL LL X Q0 HX X Z |
类似零件编号 - DM74S374N |
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类似说明 - DM74S374N |
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