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FW82371EB 数据表(PDF) 46 Page - Intel Corporation

部件名 FW82371EB
功能描述  Intel짰 82371AB PIIX4, Intel짰 82371EB PIIX4E, Intel짰 82371MB PIIX4M
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

FW82371EB 数据表(HTML) 46 Page - Intel Corporation

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Intel
® 82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
R
46
Specification Update
In the PIIX4 datasheet, Page 150, Section 7.3.3, SMBHSTCNT - SMBUS HOST CONTROL
REGISTER (IO), Bit 0 should be changed to read:
7.3.3
SMBHSTCNT—SMBUS HOST CONTROL REGISTER (IO)
I/O Address:
Base + (02h)
Default Value:
00h
Attribute:
Read/Write
The control register is used to enable SMBus controller host interface functions. Reads to this
register clears the host interface’s index pointer to the block data storage array.
Bit
Description
7
Reserved.
6
Start (START)—R/W. 1=Start execution. Writing a 1 to this bit initiates the SMBus controller host
interface to execute the command programmed in the SMB_CMD_PORT field. All necessary
registers should be setup prior to writing a 1 to this bit position. 0=Writing a 0 has no effect. This
bit always reads 0. The HOST_BUSY bit can be used to identify when the SMBus host controller
has finished executing the command.
5
Reserved.
4:2
SMBus Command Protocol (SMB_CMD_PROT)—R/W. Selects the type of command the
SMBus controller host interface will execute. Reads or writes are determined by bit 0 of
SMBHSTADD register. This field is decoded as follows:
Bits[4:2]
Protocol
Bits[4:2]
Protocol
000
Quick Read or Write
100
Reserved
001
Byte Read or Write
101
Block Read or Write
010
Byte Data Read or Write
110
Reserved
011
Word Data Read or Write
111
Reserved
1
Kill (KILL)—R/W. 1=Stop the current in process SMBus controller host transaction. This sets the
FAILED status bit and asserts the interrupt selected by the SMB_INTRSEL field. 0=Allows the
SMBus controller host interface to function normally.
0
Interrupt Enable (INTEREN)—R/W. 1= Enable the generation of interrupts (IRQ9OUT) or SMI (as
defined in the table listed in section 7.1.28., SMBUS HOST CONFIGURATION REGISTER
(Function 3), bit [3:1], SMBus Interrupt Select) on the completion of the current host transaction.
0=Disable.
In the PIIX4 datasheet, Pages 266-267, Section 11.5.4.1, SMBus Host Interface, paragraph 2
should be modified as follows:
11.5.4.1
SMBus Host Interface
A SMBus Host Controller is used to send commands to various SMBus devices. The PIIX4
SMBus controller implements a full host controller implementation. The PIIX4 SMBus controller
supports seven command protocols of the SMBus interface (see System Management Bus
Specification, Revision 1.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read
Byte/Word, Block Read, and Block Write.
To execute a SMBus host transaction, the type of transfer protocol, the address of SMBus device,
the device specific command, the data, and any control bits are first setup. Then the START bit is
set, which causes the host controller to execute the transaction. When the transaction is completed,
PIIX4 generates an interrupt, if enabled. The interrupt can be selected between IRQ9OUT and


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