ADG738/ADG739

Data Sheet

Rev. A | Page 8 of 20

Figure 5. ADG739 Pin Configuration

Table 6. ADG739 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. These devices can accommodate serial input rates of up to 30 MHz.

2

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC

goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is

transferred on the falling edges of the following clocks. Taking SYNC high updates the switch

conditions.

3

DIN

Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial

clock input.

4, 5, 6, 7

S1A, S2A, S3A, S4A

Source. May be an input or output.

8, 9

DA, DB

Drain. May be an input or output.

10, 11, 12, 13

S4B, S3B, S2B, S1B

Source. May be an input or output.

14

V

DD

Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.

15

GND

Ground Reference.

16

DOUT

Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of the input

shift register on the rising edge of SCLK. This is an open drain output, which should be pulled to

the supply with an external resistor.

SCLK

S2A

S3A

S4A

S1A

DA

S1B

DOUT

S2B

S3B

S4B

GND

DB

DIN

SYNC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ADG739

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