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EPF6024AQC208-3N 数据表(PDF) 23 Page - Altera Corporation |
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EPF6024AQC208-3N 数据表(HTML) 23 Page - Altera Corporation |
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23 / 52 page  Altera Corporation 23 FLEX 6000 Programmable Logic Device Family Data Sheet I/O Elements An IOE contains a bidirectional I/O buffer and a tri-state buffer. IOEs can be used as input, output, or bidirectional pins. An IOE receives its data signals from the adjacent local interconnect, which can be driven by a row or column interconnect (allowing any LE in the device to drive the IOE) or by an adjacent LE (allowing fast clock-to-output delays). A FastFLEXTM I/O pin is a row or column output pin that receives its data signals from the adjacent local interconnect driven by an adjacent LE. The IOE receives its output enable signal through the same path, allowing individual output enables for every pin and permitting emulation of open-drain buffers. The Altera Compiler uses programmable inversion to invert the data or output enable signals automatically where appropriate. Open- drain emulation is provided by driving the data input low and toggling the OE of each IOE. This emulation is possible because there is one OE per pin. A chip-wide output enable feature allows the designer to disable all pins of the device by asserting one pin (DEV_OE). This feature is useful during board debugging or testing. Figure 12 shows the IOE block diagram. Figure 12. IOE Block Diagram From LAB Local Interconnect Slew-Rate Control From LAB Local Interconnect To Row or Column Interconnect Chip-Wide Output Enable Delay |
类似零件编号 - EPF6024AQC208-3N |
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类似说明 - EPF6024AQC208-3N |
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