www.fairchildsemi.com

2

Truth Table

Division Ratio Table

Operating Characteristics

With Auto Reset pin set to a “0” the counter circuit is initial-

ized by turning on power. Or with power already on, the

counter circuit is reset when the Master Reset pin is set to

a “1”. Both types of reset will result in synchronously reset-

ting all counter stages independent of counter state.

The RC oscillator frequency is determined by the external

RC network, i.e.:

The time select inputs (A and B) provide a two-bit address

represent the Q output of the Nth stage of the counter.

However, when B is “0”, normal counting is interrupted and

the 9th counter stage receives its clock directly from the

The Q/Q select output control pin provides for a choice of

output level. When the counter is in a reset condition and

Q/Q select pin is set to a “0” the Q output is a “0”. Corre-

spondingly, when Q/Q select pin is set to a “1” the Q output

is a “1”.

When the mode control pin is set to a “1”, the selected

count is continually transmitted to the output. But, with

mode pin “0” and after a reset condition the RS flip-flop

resets (see Logic Diagram), counting commences and after

will not change. Thus, a Master Reset pulse must be

applied or a change in the mode pin level is required to

reset the single cycle operation.

Typical RC Oscillator

Characteristics

Solid Line

= R

f

= 10.2 kHz @ V

Dashed Line

= R

f

= 7.75 kHz @ V

RC Oscillator Frequency as a

Pin

State

01

5

Auto Reset Operating

Auto Reset Disabled

6

Timer Operational

Master Reset On

9

Output Initially Low

Output Initially High

after Reset

after Reset

10

Single Cycle Mode

Recycle Mode

Number of

Count

A

B

Counter Stages

n

0

0

13

8192

0

1

10

1024

10

8

256

1

1

16

65536