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CD4046BCMX 数据表(PDF) 11 Page - Fairchild Semiconductor |
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CD4046BCMX 数据表(HTML) 11 Page - Fairchild Semiconductor |
11 / 14 page 11 www.fairchildsemi.com Design Information This information is a guide for approximating the value of external components for the CD4046B in a phase-locked- loop system. The selected external components must be within the following ranges: R1, R2 ≥ 10 kΩ, R S ≥ 10 kΩ, C1 ≥ 50 pF. In addition to the given design information, refer to Figure 5, Figure 6, Figure 7 for R1, R2 and C1 component selec- tions. Using Phase Comparator I Using Phase Comparator II Characteristics VCO Without Offset VCO With Offset VCO Without Offset VCO With Offset R2 = ∞ R2 = ∞ VCO Frequency For No Signal Input VCO in PLL system will adjust VCO in PLL system will adjust to to center frequency, fo lowest operating frequency, fmin Frequency Lock 2 fL = full VCO frequency range Range, 2 fL 2 fL = fmax − fmin Frequency Capture Range, 2 fC Loop Filter Component Selection For 2 fC, see Ref. fC = fL Phase Angle Between 90 ° at center frequency (f o), approximating Always 0 ° in lock Single and Comparator 0 ° and 180° at ends of lock range (2 f L) Locks on Harmonics Yes No of Center Frequency Signal Input Noise High Low Rejection |
类似零件编号 - CD4046BCMX |
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类似说明 - CD4046BCMX |
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