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CD4014 数据表(PDF) 1 Page - Fairchild Semiconductor

部件名 CD4014
功能描述  8-Stage Static Shift Register
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
标志 FAIRCHILD - Fairchild Semiconductor

CD4014 数据表(HTML) 1 Page - Fairchild Semiconductor

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October 1987
Revised January 1999
© 1999 Fairchild Semiconductor Corporation
DS005947.prf
www.fairchildsemi.com
CD4014BC
8-Stage Static Shift Register
General Description
The CD4014BC is an 8-stage parallel input/serial output
shift register. A parallel/serial control input enables individ-
ual JAM inputs to each of 8 stages. Q outputs are available
from the sixth, seventh and eighth stages. All outputs have
equal source and sink current capabilities and conform to
standard “B” series output drive.
When the parallel/serial control input is in the logical “0”
state, data is serially shifted into the register synchronously
with the positive transition of the clock. When the parallel/
serial control input is in the logical “1” state, data is jammed
into each stage of the register synchronously with the posi-
tive transition of the clock.
All inputs are protected against static discharge with diodes
to VDD and VSS.
Features
s Wide supply voltage range:
3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
s 5V–10V–15V parametric ratings
s Symmetrical output characteristics
s Maximum input leakage:
1
µA at 15V over full temperature range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “x” to the ordering code.
Connection Diagram
Pin Assignments for DIP
Top View
Truth Table
X
= Don't care case
No Change
Note 1: Level change
Order Number
Package Number
Package Description
CD4014BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4014BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
CL
(Note 1)
Serial
Input
Parallel/
Serial
Control
PI 1
PI n
Q1
(Internal)
Qn

X
1
0
000

X
1
1
010

X
1
0
101

X
1
1
111

00
X
X
0
Qn−1

10
X
X
1
Qn−1

XX
X
X
Q1
Qn


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