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74VHC164M 数据表(PDF) 2 Page - Fairchild Semiconductor |
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74VHC164M 数据表(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Functional Description The VHC164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active High Enable for data entry through the other input. An unused input must be tied HIGH. Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the log- ical AND of the two data inputs (A • B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW. Function Table H HIGH Voltage Levels L LOW Voltage Levels X Immaterial Q Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Operating Inputs Outputs Mode MR AB Q0 Q1–Q7 Reset (Clear) L X X L L–L Shift H L L L Q0–Q6 HL HL Q0–Q6 HH L L Q0–Q6 HH HH Q0–Q6 |
类似零件编号 - 74VHC164M |
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类似说明 - 74VHC164M |
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