© 2005 Fairchild Semiconductor Corporation

DS500229

www.fairchildsemi.com

January 2000

Revised June 2005

74VCXH16373

Low Voltage 16-Bit Transparent Latch with Bushold

General Description

The VCXH16373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch

Enable (LE) is HIGH. When LE is LOW, the data that meets

the setup time is latched. Data appears on the bus when

the Output Enable (OE) is LOW. When OE is HIGH, the

outputs are in a high impedance state.

The VCXH16373 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level.

The 74VCXH16373 is designed for low voltage (1.2V to

The 74VCXH16373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

s 3.6V tolerant control inputs and outputs

s Bushold on data inputs eliminates the need for external

pull-up/pull-down resistors

s Uses patented noise/EMI reduction circuitry

s Latch-up performance exceeds 300 mA

s ESD performance:

Human body model

! 2000V

Machine model

! 200V

s Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Ordering Code:

Note 1: Ordering Code “G” indicates Tray.

Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number

Package Number

Package Description

74VCXH16373G

(Note 1)(Note 2)

BGA54A

(Preliminary)

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74VCXH16373MTD

(Note 2)

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide