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EP1C6F256C8N 数据表(PDF) 59 Page - Altera Corporation

部件名 EP1C6F256C8N
功能描述  Cyclone Device Handbook, Volume 1
Download  385 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1C6F256C8N 数据表(HTML) 59 Page - Altera Corporation

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Altera Corporation
2–39
May 2008
Preliminary
I/O Structure
I/O Structure
IOEs support many features, including:
Differential and single-ended I/O standards
3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Output drive strength control
Weak pull-up resistors during configuration
Slew-rate control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors in user mode
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Cyclone device IOEs contain a bidirectional I/O buffer and three registers
for complete embedded bidirectional single data rate transfer.
Figure 2–27 shows the Cyclone IOE structure. The IOE contains one input
register, one output register, and one output enable register. You can use
the input registers for fast setup times and output registers for fast
clock-to-output times. Additionally, you can use the output enable (OE)
register for fast clock-to-output enable timing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins. IOEs can be used as input, output, or
bidirectional pins.


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