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74LVX163SJ 数据表(PDF) 5 Page - Fairchild Semiconductor

部件名 74LVX163SJ
功能描述  Low Voltage Synchronous Binary Counter with Synchronous Clear
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
标志 FAIRCHILD - Fairchild Semiconductor

74LVX163SJ 数据表(HTML) 5 Page - Fairchild Semiconductor

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AC Electrical Characteristics
Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: ICC (opr) = CPD * VCC * fIN + ICC.
When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ∆ICC which is obtained from the following formula:
CQ0–CQ3 and CTC are the capacitances at Q0–Q3 and TC, respectively. FCP is the input frequency of the CP.
Symbol
Parameter
VCC
(V)
TA = 25°CTA = −40°C to +85°C
Units
Conditions
Min
Typ
Max
Min
Max
tPLH
Propagation Delay
2.7
9.0
14.0
1.0
16.0
ns
CL = 15 pF
tPHL
Time (CP–Qn)
11.3
17.0
1.0
19.0
CL = 50 pF
3.3
± 0.3
8.3
12.8
1.0
15.0
ns
CL = 15 pF
10.8
16.3
1.0
18.5
CL = 50 pF
tPLH
Propagation Delay
2.7
9.5
14.3
1.0
16.7
ns
CL = 15 pF
tPHL
Time (CP–TC, Count)
12.5
18.5
1.0
20.5
CL = 50 pF
3.3
± 0.3
8.7
13.6
1.0
16.0
ns
CL = 15 pF
11.2
17.1
1.0
19.5
CL = 50 pF
tPLH
Propagation Delay
2.7
11.4
18.0
1.0
21.0
ns
CL = 15 pF
tPHL
Time (CP–TC, Load)
14.0
21.0
1.0
24.0
CL = 50 pF
3.3
± 0.3
11.0
17.2
1.0
20.0
ns
CL = 15 pF
13.5
20.7
1.0
23.5
CL = 50 pF
tPLH
Propagation Delay
2.7
8.6
13.5
1.0
15.0
ns
CL = 15 pF
tPHL
Time (CET–TC)
11.0
16.5
1.0
18.5
CL = 50 pF
3.3
± 0.3
7.5
12.3
1.0
14.5
ns
CL = 15 pF
10.5
15.8
1.0
18.0
CL = 50 pF
fMAX
Maximum Clock
2.7
75
115
65
MHz
CL = 15 pF
Frequency
50
80
45
CL = 50 pF
3.3
± 0.3
80
130
70
MHz
CL = 15 pF
55
85
50
CL = 50 pF
CIN
Input Capacitance
4
10
10
pF
VCC = Open
CPD
Power Dissipation Capacitance
23
pF
(Note 4)


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