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74LVTH16835MTD 数据表(PDF) 2 Page - Fairchild Semiconductor |
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74LVTH16835MTD 数据表(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page Preliminary www.fairchildsemi.com 2 Connection Diagram Pin Descriptions Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance ↑ = HIGH-to-LOW Clock Transition Note 1: Output level before the indicated steady-state input conditions were established, provided that CLK was HIGH before LE went LOW. Note 2: Output level before the indicated steady-state input conditions were established. Logic Diagram Pin Names Description A1–A18 Data Register Inputs Y1–Y18 3-STATE Outputs CLK Clock Pulse Input OE Output Enable Input LE Latch Enable Input Inputs Output Y OE LE CLK A HX X X Z LH X L L LH X H H LL ↑ LL LL ↑ HH LL H X Y0 (Note 1) LL L X Y0 (Note 2) |
类似零件编号 - 74LVTH16835MTD |
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类似说明 - 74LVTH16835MTD |
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