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PC28F256J3C125 数据表(PDF) 57 Page - Intel Corporation |
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PC28F256J3C125 数据表(HTML) 57 Page - Intel Corporation |
57 / 72 page 28F256J3, 28F128J3, 28F640J3, 28F320J3 Datasheet 57 (P+5)h (P+6)h (P+7)h (P+8)h 4 Optional feature and command support (1=yes, 0=no) 36: --0A bits 9–31 are reserved; undefined bits are “0.” If bit 31 is 37: --00 “1” then another 31 bit field of optional features follows at 38: --00 the end of the bit-30 field. 39: --00 bit 0 Chip erase supported bit 0 = 0 No bit 1 Suspend erase supported bit 1 = 1 Yes bit 2 Suspend program supported bit 2 = 1 Yes bit 3 Legacy lock/unlock supported bit 3 = 1 (1) Yes (1) bit 4 Queued erase supported bit 4 = 0 No bit 5 Instant Individual block locking supported bit 5 = 0 No bit 6 Protection bits supported bit 6 = 1 Yes bit 7 Page-mode read supported bit 7 = 1 Yes bit 8 Synchronous read supported bit 8 = 0 No (P+9)h 1 Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1–7 reserved; undefined bits are “0” 3A: --01 bit 0 Program supported after erase suspend bit 0 = 1 Yes (P+A)h (P+B)h 2 Block status register mask 3B: --01 bits 2–15 are Reserved; undefined bits are “0” 3C: --00 bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes bit 1 Block Lock-Down Bit Status active bit 1 = 0 No (P+C)h 1 VCC logic supply highest performance program/erase voltage bits 0–3 BCD value in 100 mV bits 4–7 BCD value in volts 3D: --33 3.3 V (P+D)h 1 VPP optimum program/erase supply voltage bits 0–3 BCD value in 100 mV bits 4–7 HEX value in volts 3E: --00 0.0 V NOTE: 1. Future devices may not support the described “Legacy Lock/Unlock” function. Thus bit 3 would have a value of “0.” Table 30. Primary Vendor-Specific Extended Query (Sheet 2 of 2) Offset (1) P = 31h Length Description (Optional Flash Features and Commands) Add. Hex Code Value |
类似零件编号 - PC28F256J3C125 |
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类似说明 - PC28F256J3C125 |
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