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ADV7610BBCZ-RL 数据表(PDF) 3 Page - Analog Devices |
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ADV7610BBCZ-RL 数据表(HTML) 3 Page - Analog Devices |
3 / 16 page Data Sheet ADV7610 Rev. 0 | Page 3 of 16 GENERAL DESCRIPTION The ADV7610 is offered in professional (no HDCP) and industrial versions. The operating temperature range is −40°C to +85°C. The ADV7610 is a high quality, single input HDMI-capable receiver. It incorporates an HDMI-capable receiver that supports all mandatory 3D TV defined in HDMI specification. The ADV7610 supports formats up to UXGA 60 Hz at eight bits. It integrates a CEC controller that supports the capability discovery and control (CDC) feature. The ADV7610 has a 4-channel stereo audio output port for the audio data extracted from the HDMI stream. The HDMI receiver has an advanced mute controller that prevents audible extraneous noise in the audio output. The following audio formats are accessible: • Four streams from the I2S serializer (eight channels) • A stream from the S/PDIF serializer (two uncompressed channels or N compressed channels, for example, AC3) • A DST stream The HDMI port has dedicated 5 V detect and Hot Plug assert pins. The HDMI receiver also includes an integrated equalizer that ensures the robust operation of the interface with long cables. The ADV7610 contains one main component processor (CP) that processes the video signals from the HDMI receiver. It provides features such as contrast, brightness, saturation adjustments, STDI detection block, free run, and synchronization alignment controls. Fabricated in an advanced CMOS process, the ADV7610 is provided in a 6 mm × 6 mm, 76-ball CSP_BGA, RoHS-compliant package and is specified over the −40°C to +85°C temperature range. DETAILED FUNCTIONAL BLOCK DIAGRAM CONTROL INTERFACE I2C CONTROL AND DATA PLL EDID REPEATER CONTROLLER HDCP ENGINE PACKET/ INFOFRAME MEMORY 12 12 12 BACKEND COLORSPACE CONVERSION COMPONENT PROCESSOR 5V DETECT AND HPD CONTROLLER AUDIO PROCESSOR DATA PREPROCESOR AND COLOR- SPACE CONVERSION HDMI PROCESSOR PACKET PROCESSOR A B C MUTE INTERRUPT CONTROLLER (INT1, INT2) P0 TO P7 *INT2 CAN BE OUTPUT ON ONE OF THE FOLLOWING PINS ONLY: SCLK/INT2, MCLK/INT2, OR HPA_A/INT2. XTALP XTALN SCL SDA CEC RXA_5V HPA_A/INT2* DDCA_SDA DDCA_SCL RXA_C± RXA_0± RXA_1± RXA_2± P8 TO P15 P16 TO P23 LLC HS VS/FIELD/ALSB DE INT1 INT2* LRCLK SCLK/INT2* MCLK/INT2* 4 I2S0 TO I2S3 HDCP EEPROM SAMPLER EQUALIZER DPLL CEC CONTROLLER ADV7610 Figure 2. Detailed Functional Block Diagram |
类似零件编号 - ADV7610BBCZ-RL |
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类似说明 - ADV7610BBCZ-RL |
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