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AD5313RBRUZ-RL7 数据表(PDF) 3 Page - Analog Devices

部件名 AD5313RBRUZ-RL7
功能描述  Dual, 10-Bit nanoDAC with 2 ppm/C Reference, SPI Interface
Download  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5313RBRUZ-RL7 数据表(HTML) 3 Page - Analog Devices

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Data Sheet
AD5313R
Rev. 0 | Page 3 of 28
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE1
Resolution
10
Bits
Relative Accuracy
±0.12
±0.5
LSB
Differential Nonlinearity
±0.5
LSB
Guaranteed monotonic by design
Zero-Code Error
0.4
1.5
mV
All 0s loaded to DAC register
Offset Error
+0.1
±1.5
mV
Full-Scale Error
+0.01
±0.1
% of FSR
All 1s loaded to DAC register
Gain Error
±0.02
±0.1
% of FSR
Total Unadjusted Error
±0.01
±0.1
% of FSR
External reference; gain = 2; TSSOP
±0.2
% of FSR
Internal reference; gain = 1; TSSOP
Offset Error Drift2
±1
µV/°C
Gain Temperature Coefficient2
±1
ppm
Of FSR/°C
DC Power Supply Rejection Ratio2
0.15
mV/V
DAC code = midscale; VDD = 5 V ± 10%
DC Crosstalk2
±2
µV
Due to single-channel, full-scale output change
±3
µV/mA
Due to load current change
±2
µV
Due to powering down (per channel)
OUTPUT CHARACTERISTICS2
Output Voltage Range
0
VREF
V
Gain = 1
0
2 × VREF
V
Gain = 2; see Figure 29
Capacitive Load Stability
2
nF
RL = ∞
10
nF
RL = 1 kΩ
Resistive Load3
1
Load Regulation
80
µV/mA
5 V ± 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ 30 mA
80
µV/mA
3 V ± 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ 20 mA
Short-Circuit Current4
40
mA
Load Impedance at Rails5
25
Ω
See Figure 29
Power-Up Time
2.5
µs
Coming out of power-down mode; VDD = 5 V
REFERENCE OUTPUT
Output Voltage6
2.4975
2.5025
V
At ambient
Reference Temperature Coefficient7, 8
2
5
ppm/°C
See the Terminology section
Output Impedance2
0.04
Ω
Output Voltage Noise2
12
µV p-p
0.1 Hz to 10 Hz
Output Voltage Noise Density2
240
nV/√Hz
At ambient; f = 10 kHz, CL = 10
nF
Load Regulation Sourcing2
20
µV/mA
At ambient
Load Regulation Sinking2
40
µV/mA
At ambient
Output Current Load Capability2
±5
mA
VDD ≥ 3 V
Line Regulation2
100
µV/V
At ambient
Long-Term Stability/Drift2
12
ppm
After 1000 hours at 125°C
Thermal Hysteresis2
125
ppm
First cycle
25
ppm
Additional cycles
LOGIC INPUTS2
Input Current
±2
µA
Per pin
Input Low Voltage (VINL)
0.3 × VLOGIC
V
Input High Voltage (VINH)
0.7 × VLOGIC
V
Pin Capacitance
2
pF


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