EPM3064ATI44-10N datasheet(37/46 Pages) ALTERA

部件名	EPM3064ATI44-10N

功能描述	Built?밿n boundary-scan test circuitry compliant with

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制造商	ALTERA [Altera Corporation]

网页	http://www.altera.com

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Altera Corporation

37

MAX 3000A Programmable Logic Device Family Data Sheet

tAH

Array clock hold time

(2)

0.2

0.3

ns

tACO1

Array clock to output delay

C1 = 35 pF (2)

1.0

7.8

1.0

10.4

ns

tACH

Array clock high time

3.0

4.0

ns

tACL

Array clock low time

3.0

4.0

ns

tCPPW

Minimum pulse width for clear

and preset

(3)

3.0

4.0

ns

tCNT

Minimum global clock period

(2)

8.6

11.5

ns

fCNT

Maximum internal global clock

frequency

(2), (4)

116.3

87.0

MHz

tACNT

Minimum array clock period

(2)

8.6

11.5

ns

fACNT

Maximum internal array clock

frequency

(2), (4)

116.3

87.0

MHz

Table 25. EPM3512A Internal Timing Parameters (Part 1 of 2)

Note (1)

Symbol

Parameter

Conditions

Speed Grade

Unit

-7

-10

Min

Max

Min

Max

tIN

Input pad and buffer delay

0.7

0.9

ns

tIO

I/O input pad and buffer delay

0.7

0.9

ns

tFIN

Fast input delay

3.1

3.6

ns

tSEXP

Shared expander delay

2.7

3.5

ns

tPEXP

Parallel expander delay

0.4

0.5

ns

tLAD

Logic array delay

2.2

2.8

ns

tLAC

Logic control array delay

1.0

1.3

ns

tIOE

Internal output enable delay

0.0

ns

tOD1

Output buffer and pad delay,

slow slew rate = off

VCCIO = 3.3 V

C1 = 35 pF

1.0

1.5

ns

tOD2

Output buffer and pad delay,

slow slew rate = off

VCCIO = 2.5 V

C1 = 35 pF

1.5

2.0

ns

Table 24. EPM3512A External Timing Parameters

Note (1)

Symbol

Parameter

Conditions

Speed Grade

Unit

-7

-10

Min

Max

Min

Max

类似零件编号 - EPM3064ATI44-10N

制造商	部件名	数据表	功能描述
Altera Corporation	EPM3064ATI44-10N	715Kb / 46P	Programmable Logic Device Family

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