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LTC2970 数据表(PDF) 16 Page - Linear Technology |
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LTC2970 数据表(HTML) 16 Page - Linear Technology |
16 / 32 page LTC2945 16 2945f APPLICATIONS INFORMATION Stuck-Bus Reset The LTC2945 I2C interface features a stuck bus reset timer to prevent it from holding the bus lines low indefinitely if the SCL signal is interrupted during a transfer. The timer starts when either SCL or SDAI is low, and resets when both SCL and SDAI are pulled high. If either SCL or SDAI are low for over 33ms, the stuck-bus timer will expire and the internal I2C interface and the SDAO pin pulldown logic will be reset to release the bus. Normal communication will resume at the next Start command. Acknowledge The acknowledge signal is used for handshaking between the transmitter and the receiver to indicate that the last byte of data was received. The transmitter always releases the SDA line during the acknowledge clock pulse. The LTC2945 will pull the SDA line low on the 9th clock cycle to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA high, then the master can abort the transmission by generating a Stop condition. When the master is receiving data from the slave, the master must acknowledge the slave by pulling down the SDA line during the 9th clock pulse to indicate receipt of a data byte. After the last byte has been received by the master, it will leave the SDA line high (not acknowledge) and issue a Stop condition to terminate the transmission. Write Protocol The master begins a write operation with a Start condition followed by the seven-bit slave address and the R/W bit set to zero. After the addressed LTC2945 acknowledges the address byte, the master then sends a command byte that indicates which internal register the master wishes to write. The LTC2945 acknowledges this and then latches the lower six bits of the command byte into its internal register address pointer. The master then delivers the data byte and the LTC2945 acknowledges once more and writes the data into the internal register pointed to by the register address pointer. If the master continues sending additional data bytes with a Write Word or extended Write command, the additional data bytes will be acknowledged by the LTC2945, the register address pointer will automatically increment by one, and data will be written as above. The write operation terminates and the register address pointer resets to 00h when the master sends a Stop condition. Read Protocol The master begins a read operation with a Start condition followed by the 7-bit slave address and the R/W bit set to zero. After the addressed LTC2945 acknowledges the address byte, the master then sends a command byte that indicates which internal register the master wishes to read. The LTC2945 acknowledges this and then latches the lower six bits of the command byte into its internal register address pointer. The master then sends a repeated Start condition followed by the same 7-bit address with the R/W bit now set to 1. The LTC2945 acknowledges and sends the contents of the requested register. The transmission terminates when the master sends a Stop condition. If the master acknowledges the transmitted data byte, as in a Read Word command, the LTC2945 will send the contents of the next register. If the master keeps acknowledging, the LTC2945 will keep incrementing the register address pointer and sending out data bytes. The read operation terminates and the register address pointer resets to 00h when the master sends a Stop condition. Alert Response Protocol When any of the fault bits in the FAULT register are set, a bus alert is generated if the appropriate bit in the ALERT register has been set. This allows the bus master to select which faults will generate alerts. At power-up, the ALERT register is cleared (no alerts enabled) and the ALERT pin is high. If an alert is enabled, the corresponding fault causes the ALERT pin to pull low. The bus master responds to the alert in accordance with the SMBus alert response protocol by broadcasting the Alert Response Address (0001100)b, and the LTC2945 replies with its own address and releases its ALERT pin as shown in Figure 12. The ALERT line is also released if the FAULT or FAULT CoR registers are read (see Table 2) since the faulting event can be identified by the content in these registers. The ALERT signal is not pulled low again until the Fault register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults will not generate additional alerts until the associated FAULT register bits have been cleared. |
类似零件编号 - LTC2970 |
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类似说明 - LTC2970 |
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