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DAC8248 Datasheet(数据表) 5 Page - Analog Devices

部件型号  DAC8248
说明  Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter
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制造商  AD [Analog Devices]
网页  http://www.analog.com
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DAC8248
–5–
REV. B
11. AGND
13. NC
12. IOUTA
14. DB1
13. RFB A
15. DB0(LSB)
14. VREF A
16. RESET
15. DGND
17. LSB/MSB
16. DB7(MSB)
18. DAC A/DAC B
17. DB6
19. LDAC
18. DB5
20. WR
19. DB4
21. VDD
10. DB3
22. VREF B
11. DB2
23. RFB B
12. NC
24. IOUT B
SUBSTRATE (DIE BACKSIDE) IS INTERNALLY
CONNECTED TO VDD.
DICE CHARACTERISTICS
WAFER TEST LIMITS @ V
DD = +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; TA = 25 C.
DAC8248G
Parameter
Symbol
Conditions
Limit
Units
Relative Accuracy
INL
Endpoint Linearity Error
±1
LSB max
Differential Nonlinearity
DNL
All Grades are Guaranteed Monotonic
±1
LSB max
Full-Scale Gain Error
1
GFSE
Digital Inputs = 1111 1111 1111
±4
LSB max
Output Leakage
Digital Inputs = 0000 0000 0000
(IOUT A, IOUT B)ILKG
Pads 2 and 24
±50
nA max
Input Resistance
(VREF A, VREF B)RREF
Pads 4 and 22
8/15
k
Ω min/kΩ max
VREF A, VREF B Input
∆R
REF
Resistance Match
RREF
±1
% max
Digital Input High
VINH
VDD = +5 V
2.4
V min
VDD = +15 V
13.5
V min
Digital Input Low
VINL
VDD = +5 V
0.8
V max
VDD = +15 V
1.5
V max
Digital Input Current
IIN
VIN = 0 V or VDD; VINL or VINH
±1
µA max
Supply Current
IDD
All Digital Inputs VINL or VINH
2
mA max
All Digital Inputs 0 V or VDD
0.1
mA max
DC Supply Rejection
(
∆Gain/∆V
DD)
PSR
∆V
DD =
±5%
0.002
%/% max
NOTES
1Measured using internal R
FB A and RFB B.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
Die Size 0.124
× 0.132 inch, 16,368 sq. mils
(3.15
× 3.55 mm, 10.56 sq. mm)




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