REV. A

ADXL202E

–9–

low-pass filtering for antialiasing and noise reduction. The equa-

tion for the 3 dB bandwidth is:

=

1

2

π (32 kΩ) × C(x, y)

()

5

µF

much as

±15% of its nominal value of 32 kΩ; so the bandwidth

will vary accordingly. A minimum capacitance of 1000 pF for

Capacitor

Bandwidth

Value

10 Hz

0.47

µF

50 Hz

0.10

µF

100 Hz

0.05

µF

200 Hz

0.027

µF

500 Hz

0.01

µF

5 kHz

0.001

µF

The period of the DCM output is set for both channels by a single

T 2

=

Ω)

125 M

Ω

A 125 k

Ω resistor will set the duty cycle repetition rate to approxi-

mately 1 kHz, or 1 ms. The device is designed to operate at duty

cycle periods between 0.5 ms and 10 ms.

Table II. Resistor Values to Set T2

T2

1 ms

125 k

Ω

2 ms

250 k

Ω

5 ms

625 k

Ω

10 ms

1.25 M

Ω

Ω

and 2 M

Ω when taking the output from X

resistor should be place close to the T2 Pin to minimize parasitic

capacitance at this node.

Selecting the Right Accelerometer

For most tilt sensing applications the ADXL202E is the most

appropriate accelerometer. Its higher sensitivity (12.5%/g) allows

the user to use a lower speed counter for PWM decoding while

maintaining high resolution. The ADXL210 should be used in

applications where accelerations of greater than

±2 g are expected.

DESIGN PROCEDURE FOR THE ADXL202E

The design procedure for using the ADXL202E with a duty cycle

output involves selecting a duty cycle period and a filter capacitor.

A proper design will take into account the application requirements

for bandwidth, signal resolution and acquisition time, as discussed

in the following sections.

A 0.1

µF capacitor is recommended from V

supply decoupling.

ST

The ST pin controls the self-test feature. When this pin is set to

eter. The resulting movement of the beam allows the user to test if

the accelerometer is functional. The typical change in output will

be 10% at the duty cycle outputs (corresponding to 800 mg).

This pin may be left open circuit or connected to common in

normal use.

Duty Cycle Decoding

The ADXL202E’s digital output is a duty cycle modulator.

Acceleration is proportional to the ratio T1/T2. The nominal

output of the ADXL202E is:

0 g = 50% Duty Cycle

Scale factor is 12.5% Duty Cycle Change per g

These nominal values are affected by the initial tolerance of the

device including zero g offset error and sensitivity error.

T2 does not have to be measured for every measurement cycle.

It need only be updated to account for changes due to tempera-

ture, (a relatively slow process). Since the T2 time period is shared

by both X and Y channels, it is necessary only to measure it on

one channel of the ADXL202E. Decoding algorithms for various

microcontrollers have been developed. Consult the appropriate

Application Note.

ANALOG

TO

DUTY

CYCLE

(ADC)

C

O

U

N

T

E

R

P

DEMOD

DEMOD

32k

32k

ADXL202E

T2

SELF-TEST

OSCILLATOR

COM

Y SENSOR

X SENSOR

3V TO 5.25V

T1

T2

A(g) = (T1/T2 – 0.5)/12.5%

0g = 50% DUTY CYCLE

Figure 3. Block Diagram