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ADV7202 数据表(PDF) 4 Page - Analog Devices |
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ADV7202 数据表(HTML) 4 Page - Analog Devices |
4 / 26 page REV. PrB PRELIMINARY TECHNICAL DATA –4– ADV7202–SPECIFICATIONS Parameter Min Typ Max Unit Condition 2 PROGRAMMABLE GAIN AMPLIFIER Video ADC Gain –6 +6 dB Setup Conditions CLAMP CIRCUITRY 3 Clamp Off Leakage Current TBD µA Clamp Fine Source/Sink Current 3 µA Clamp Coarse Source/Sink Current 0.5 mA CLOCK CONTROL 4 DACCLK0/1 6, 7 27 MHz Dual CLK Dual Edge Mode DACCLK1 80 MHz Single Edge Single Clock Mode DACCLK1 8 27 MHz 4:2:2 Mode Data Setup Time, t12 2 ns All Input Modes Data Hold Time, t13 2ns Pipeline Delay 5, t 18 Video ADC TBD Clock Cycles SAR TBD Clock Cycles RESET CONTROL RESET Low Time 10 ns NOTES 1Temperature range T MIN to TMAX: 0 oC to 70oC. 2The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range. 3External clamp capacitor = 0.1 µF. 4TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤10 pF. 5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full scale transition. 6Maximum clock speed determined by setup and hold conditions. 7Single DAC only. 8Guaranteed by Characterization. Specifications subject to change without notice. 5 V SPECIFICATIONS (AVDD/DVDD = 4.75 – 5.25, V REF = 1.235 V RSET = 1.2 k , all specifications TMIN to TMAX 1 unless otherwise noted.) |
类似零件编号 - ADV7202 |
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类似说明 - ADV7202 |
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