ADV7197KST datasheet(5/20 Pages) AD

部件名	ADV7197KST

功能描述	Multiformat HDTV Encoder with Three 11-Bit DACs

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REV. 0

–5–

ADV7197

3.3 V TIMING–SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

Conditions

MPU PORT

1

SCLOCK Frequency

10

400

kHz

SCLOCK High Pulsewidth, t1

0.6

µs

SCLOCK Low Pulsewidth, t2

1.3

µs

Hold Time (Start Condition), t3

0.6

µs

After This Period the 1st Clock Is Generated

Setup Time (Start Condition), t4

0.6

µs

Relevant for Repeated Start Condition

Data Setup Time, t5

100

ns

SDATA, SCLOCK Rise Time, t6

300

ns

SDATA, SCLOCK Fall Time, t7

300

ns

Setup Time (Stop Condition), t8

0.6

µs

RESET Low Time

100

ns

ANALOG OUTPUTS

2

Analog Output Delay

10

ns

Analog Output Skew

0.5

ns

CLOCK CONTROL AND PIXEL PORT

3

fCLK

74.25

MHz

HDTV Mode

tCLK

81

MHz

Async Timing Mode

Clock High Time, t9

51.5

ns

Clock Low Time, t10

52.0

ns

Data Setup Time, t11

2.0

ns

Data Hold Time, t12

4.5

ns

Control Setup Time, t11

7ns

Control Hold Time, t12

4.0

ns

Pipeline Delay

16

Clock Cycles

For 4:4:4 Pixel Input Format

NOTES

1Guaranteed by characterization.

2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

3Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control:

HSYNC/SYNC, VSYNC/TSYNC; DV

Specifications subject to change without notice.

(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470

, RLOAD = 300

. All specifications

TMIN to TMAX [0 C to 70 C] unless otherwise noted.)

CLOCK

PIXEL INPUT

DATA

Y0

Cb0

Y1

Cr0

Y2

Cb1

Cr1

...

Yxxx

Cbxxx

Yxxx

Crxxx

t11

t12

t9

t10

t9 – CLOCK HIGHTIME

t10 – CLOCK LOWTIME

t11 – DATA SETUPTIME

t12 – DATA HOLDTIME

Figure 1. 4:2:2 Input Data Format Timing Diagram

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制造商	部件名	数据表	功能描述
Analog Devices	ADV7197	252Kb / 20P	Multiformat HDTV Encoder with Three 11-Bit DACs REV. 0

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