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ADV7127KR50 数据表(PDF) 6 Page - Analog Devices |
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ADV7127KR50 数据表(HTML) 6 Page - Analog Devices |
6 / 16 page –6– REV. 0 ADV7127–SPECIFICATIONS 5 V/3.3 V DYNAMIC SPECIFICATIONS Parameter Min Typ Max Units DAC PERFORMANCE Glitch Impulse 2, 3 10 pVs Data Feedthrough 2, 3 22 dB Clock Feedthrough 2, 3 33 dB NOTES 1These max/min specifications are guaranteed by characterization. 2TTL input values are for 0 V and 3 V with input rise/fall times ≤3 ns, measured at the 10% and 90% points. Timing reference points at 50% for inputs and outputs. 3Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. Specifications subject to change without notice. (VAA = (3 V–5.25 V) 1, V REF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications are for TA = +25 C unless otherwise noted, TJ MAX = 110 C) 5 V TIMING SPECIFICATIONS1 Parameter Min Typ Max Units Condition ANALOG OUTPUTS Analog Output Delay, t6 5.5 ns Analog Output Rise/Fall Time, t7 4 1.0 ns Analog Output Transition Time, t8 5 15 ns Analog Output Skew, t9 6 12 ns CLOCK CONTROL fCLK 7 0.5 50 MHz 50 MHz Grade fCLK 7 0.5 140 MHz 140 MHz Grade fCLK 7 0.5 240 MHz 240 MHz Grade Data and Control Setup, t1 1.5 ns Data and Control Hold, t2 2.5 ns Clock Pulsewidth High, t4 1.875 1.1 ns fMAX = 240 MHz Clock Pulsewidth Low t5 1.875 1.25 ns fMAX = 240 MHz Clock Pulsewidth High t4 2.85 ns fMAX = 140 MHz Clock Pulsewidth Low t5 2.85 ns fMAX = 140 MHz Clock Pulsewidth High t4 8.0 ns fMAX = 50 MHz Clock Pulsewidth Low t5 8.0 ns fMAX = 50 MHz Pipeline Delay, tPD 6 1.0 1.0 1.0 Clock Cycles PSAVE Up Time, t10 6 210 ns PDOWN Up Time, t11 8 320 ns NOTES 1Timing specifications are measured with input levels of 3.0 V (V IH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies. 2These maximum and minimum specifications are guaranteed over this range. 3Temperature range: T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz. 4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5Measured from 50% point of full-scale transition to 2% of final value. 6Guaranteed by characterization. 7f CLK max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization. 8This power-down feature is only available on the ADV7127 in the TSSOP package. Specifications subject to change without notice. (VAA = +5 V 5% 2, V REF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications TMIN to TMAX 3 unless otherwise noted, TJ MAX = 110 C) |
类似零件编号 - ADV7127KR50 |
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类似说明 - ADV7127KR50 |
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