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ADSP-21065LKCA-264 数据表(PDF) 2 Page - Analog Devices |
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ADSP-21065LKCA-264 数据表(HTML) 2 Page - Analog Devices |
2 / 44 page REV. C ADSP-21065L –2– 544 Kbits Configurable On-Chip SRAM Dual-Ported for Independent Access by Core Processor and DMA Configurable in Combinations of 16-, 32-, 48-Bit Data and Program Words in Block 0 and Block 1 DMA Controller Ten DMA Channels—Two Dedicated to the External Port and Eight Dedicated to the Serial Ports Background DMA Transfers at up to 66 MHz, in Parallel with Full Speed Processor Execution Performs Transfers Between: Internal RAM and Host Internal RAM and Serial Ports Internal RAM and Master or Slave SHARC Internal RAM and External Memory or I/O Devices External Memory and External Devices Host Processor Interface Efficient Interface to 8-, 16-, and 32-Bit Microprocessors Host Can Directly Read/Write ADSP-21065L IOP Registers Multiprocessing Distributed On-Chip Bus Arbitration for Glueless, Parallel Bus Connect Between Two ADSP-21065Ls Plus Host 132 Mbytes/s Transfer Rate Over Parallel Bus Serial Ports Independent Transmit and Receive Functions Programmable 3-Bit to 32-Bit Serial Word Width I2S Support Allowing Eight Transmit and Eight Receive Channels Glueless Interface to Industry Standard Codecs TDM Multichannel Mode with -Law/A-Law Hardware Companding Multichannel Signaling Protocol |
类似零件编号 - ADSP-21065LKCA-264 |
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类似说明 - ADSP-21065LKCA-264 |
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