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ADSP-2141LKS-N1 数据表(PDF) 7 Page - Analog Devices |
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ADSP-2141LKS-N1 数据表(HTML) 7 Page - Analog Devices |
7 / 39 page REV. 0 ADSP-2141L –7– If the AllowRedKeyLoad bit is set, keys may be loaded either in their black form, or in the red or unencrypted form. Note that the laser configuration bit may be overridden with a signed enabler token. (For more information, see the Laser Variable Storage section.) Depending on the definition of the security module boundary in a given application, FIPS 140-1 may require the use of black keys to protect key material. In other words, if the security boundary does not enclose the database where keys are stored, those keys must be protected from compromise. Black key is a satisfactory way to meet this FIPS requirement. Random Number Generator (RNG) Block The random number generator is designed to provide highly random, nondeterministic binary numbers at a high delivery rate with little software intervention. The random numbers are acces- sible to the kernel firmware in a 16-bit register that may be read by the DSP in kernel mode. Once the register is read, the RNG immediately generates a new 16-bit value that is available within 12 microseconds. All application-level access to random numbers should occur through the Kernels CGX_RANDOM command (see the Command Summary section). The random number generator is designed using a “shot noise” true entropy source which is sampled by the master 40 MHz clock of the ADSP-2141L. The entropy source then feeds a complex nonlinear combinatorial circuit that produces the final RNG output based on the interaction of the entropy source and the 40 MHz system clock. Over 200 stages of Linear Feedback Shift Register (LFSR) are incorporated into the RNG design. In order to facilitate FIPS 140-1 compliance, an option may be selected during CGX kernel initialization to enable an ANSI X9.17 Annex C post-randomizer to be applied to the output of the RNG. This randomizer applies the DES ECB algorithm multiple times to further disperse and whiten the random source. Although this is not necessary to ensure the quality of the random numbers, it meets the criteria for a NIST-approved random num- ber generation algorithm. Public Key Accelerator (PKAC) The public key arithmetic coprocessor (otherwise known as a BigNum processor) is designed to support long vector calcula- tions of the kind needed to perform RSA, Diffie-Hellman and Elliptic Curve operations. The PKAC can perform multiplication, squaring, addition and subtraction on arbitrary length bit vectors. The CGX software is responsible for setting the address register for the operands and result, as well as specifying the length and operation type. Once the operation type field is written, the processor polls the opera- tion complete status while the calculation is carried out. The PKAC utilizes the protected kernel RAM for input, output and intermediate variable storage. It may only be accessed from the secure kernel mode. Since public key computations typically take many milliseconds to complete, they may be preempted using a DSP interrupt. Most application interaction with the public key accelerator will occur via the CGX software interface (see the Command Inter- face section). Both high level public key operations such as RSA Sign or Create Diffie-Hellman Key, as well as primitive operations such as Multiply Vector, Add Long Vector, etc., are presented via the CGX interface. PCI/Cardbus Interface The ADSP-2141L appears as a target on the PCI Bus as a single contiguous memory space of 128k bytes. In this memory space, the host can access the following: • The unprotected internal crypto registers of the ADSP-2141L • IDMA access to the DSP’s internal program memory (PM) and data memory (DM) • Paged access to external memory connected to the ADSP-2141L • The Kernel RAM (KRAM) if it has been unprotected by an extended mode program As a PCI Master, the ADSP-2141L can transfer data between: • The unprotected internal crypto registers and FIFOs of the ADSP-2141L and PCI Host memory • External memory and PCI Host memory A 32-bit DMA engine within the ADSP-2141L facilitates these transfers and permits full PCI bandwidth use. Serial EEPROM Interface The serial EEPROM interface allows the ADSP-2141L to auto- matically read the PCI configuration parameters at chip power-up. IRE can provide the data content for the EEPROM to properly set the chip device vendor ID, type and properties for full com- pliance with the PCI Plug and Play standards. In addition to being used for storage of host bus parameters, any extra space in the EEPROM may be accessed by the DSP, either in user mode or kernel mode. Support for this function is not included in the standard CGX command set. Refer to the ADSP-2141 User’s Manual for the information on the data contents of the EEPROM. Refer to http://www.analog.com/ industry/dsp/ire.html. Table I. Interrupt Sources Internal Interrupt Sources External Interrupt Sources Interrupt Notes Interrupt Notes Reset or Power-Up (PUCR = 1) IRQ2 Edge- or Level-Sensitive Power-Down IRQL1 Level-Sensitive SPORT0 Transmit IRQL0 Level-Sensitive SPORT0 Receive IRQE Edge-Sensitive BDMA Interrupt IRQ1 Edge- or Level-Sensitive SPORT1 Transmit Mixed with IRQ1 IRQ0 Edge- or Level-Sensitive SPORT1 Receive Mixed with IRQ0 Timer |
类似零件编号 - ADSP-2141LKS-N1 |
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类似说明 - ADSP-2141LKS-N1 |
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