This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

11

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

REDY

O (O/D)

Host Bus Acknowledge. The ADSP-21160N deasserts REDY (low) to add waitstates

to a host access when

CS and HBR inputs are asserted.

DMAR1

I/A

DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA

services.

DMAR1 has a 20k

Ω internal pull-up resistor that is enabled on the

ADSP-21160N with ID2–0 = 00x.

DMAR2

I/A

DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA

services.

DMAR2 has a 20k

Ω internal pull-up resistor that is enabled on the

ADSP-21160N with ID2–0 = 00x.

ID2–0

I

Multiprocessing ID. Determines which multiprocessing bus request (

BR1–BR6) is used

by ADSP-21160N. ID = 001 corresponds to

BR1, ID = 010 corresponds to BR2, and

so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system

configuration selection which should be hardwired or only changed at reset.

DMAG1

O/T

DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160N to indicate that the

requested DMA starts on the next cycle. Driven by bus master only.

DMAG1 has a

20k

Ω internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

DMAG2

O/T

DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160N to indicate that the

requested DMA starts on the next cycle. Driven by bus master only.

DMAG2 has a

20k

Ω internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.

BR6–1

I/O/S

Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160Ns to arbitrate

for bus mastership. An ADSP-21160N only drives its own

BRx line (corresponding to

the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with

less than six ADSP-21160Ns, the unused

BRx pins should be pulled high; the processor’s

own

BRx line must not be pulled high or low because it is an output.

RPBA

I/S

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for

multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected.

This signal is a system configuration selection which must be set to the same value on

every ADSP-21160N. If the value of RPBA is changed during system operation, it must

be changed in the same CLKIN cycle on every ADSP-21160N.

PA

I/O/T

Priority Access. Asserting its

PA pin allows an ADSP-21160N bus slave to interrupt

background DMA transfers and gain access to the external bus.

PA is connected to all

ADSP-21160Ns in the system. If access priority is not required in a system, the

PA pin

should be left unconnected.

PA has a 20k

Ω internal pull-up resistor that is enabled on

the ADSP-21160N with ID2–0 = 00x.

DTx

O

Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k

Ω internal pull-up resistor.

DRx

I

Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k

Ω internal pull-up resistor.

TCLKx

I/O

Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k

Ω internal pull-up resistor.

RCLKx

I/O

Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k

Ω internal pull-up resistor.

TFSx

I/O

Transmit Frame Sync (Serial Ports 0, 1).

RFSx

I/O

Receive Frame Sync (Serial Ports 0, 1).

LxDAT7–0

I/O

Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 k

Ω internal pull-down

resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.

LxCLK

I/O

Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 k

Ω internal pull-down

resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.

LxACK

I/O

Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 k

Ω internal

pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.

EBOOT

I

EPROM Boot Select. For a description of how this pin operates, see Table 3. This signal

is a system configuration selection that should be hardwired.

LBOOT

I

Link Boot. For a description of how this pin operates, see Table 3. This signal is a system

configuration selection that should be hardwired.

BMS

I/O/T

Boot Memory Select. Serves as an output or input as selected with the EBOOT and

LBOOT pins; see Table 3. This input is a system configuration selection that should be

hardwired.

Table 2. Pin Function Descriptions (Continued)

Pin

Type

Function