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ADMC300 数据表(PDF) 8 Page - Analog Devices |
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ADMC300 数据表(HTML) 8 Page - Analog Devices |
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8 / 42 page  ADMC300 –8– REV. B DSP CORE ARCHITECTURE OVERVIEW Figure 3 is an overall block diagram of the DSP core of the ADMC300, which is based on the fixed-point ADSP-2171. The ADSP-2171 flexible architecture and comprehensive instruction set allows the processor to perform multiple operations in paral- lel. In one processor cycle (40 ns with a 12.5 MHz CLKIN) the DSP core can: • Generate the next program address. • Fetch the next instruction. • Perform one or two data moves. • Update one or two data address pointers. • Perform a computational operation. This all takes place while the processor continues to: • Receive and transmit through the serial ports. • Decrement the interval timer. • Generate PWM signals. • Convert the ADC input signals. • Operate the encoder interface unit. • Operate all other peripherals including the auxiliary PWM and event timer subsystem. The processor contains three independent computational units: the arithmetic and logic unit (ALU), the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, multiply/ subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormal- ization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control including floating- point representations. The internal result (R) bus directly connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computa- tional units. The sequencer supports conditional jumps and subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADMC300 executes looped code with zero overhead; no explicit jump instructions are required to maintain the loop. BUS EXCHANGE DATA ADDRESS GENERATOR #2 DATA ADDRESS GENERATOR #1 14 14 24 16 6 R BUS 16 COMPANDING CIRCUITRY DMA BUS PMA BUS DMD BUS PMD BUS PROGRAM SEQUENCER INSTRUCTION REGISTER INPUT REGS OUTPUT REGS SHIFTER INPUT REGS OUTPUT REGS MAC INPUT REGS OUTPUT REGS ALU SERIAL PORT 0 RECEIVE REG TRANSMIT REG CONTROL LOGIC DM RAM 1K 16 PM ROM 2K 24 PM RAM 4K 24 SERIAL PORT 1 RECEIVE REG TRANSMIT REG 5 TIMER Figure 3. DSP Core Block Diagram |
类似零件编号 - ADMC300 |
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类似说明 - ADMC300 |
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