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ADM1020AR-REEL7 数据表(PDF) 2 Page - Analog Devices |
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ADM1020AR-REEL7 数据表(HTML) 2 Page - Analog Devices |
2 / 12 page REV. 0 –2– ADM1020–SPECIFICATIONS (T A = TMIN to TMAX, VDD = 3.0 V to 3.6 V, unless otherwise noted) Parameter Min Typ Max Units Test Conditions/Comments POWER SUPPLY AND ADC Temperature Resolution 1 °C Guaranteed No Missed Codes Temperature Error, Local Sensor ±1 °C –3 +3 °C Temperature Error, Remote Sensor –3 +3 °CT A = +60 °C to +100°C –5 +5 °C Supply Voltage Range 3 3.6 V Note 1 Undervoltage Lockout Threshold 2.5 2.7 2.95 V VDD Input, Disables ADC, Rising Edge Undervoltage Lockout Hysteresis 25 mV Power-On Reset Threshold 0.9 1.7 2.2 V VDD, Falling Edge 2 POR Threshold Hysteresis 50 mV Standby Supply Current 3 10 µAV DD = 3.3 V, No SMBus Activity 4 µA SCLK at 10 kHz Average Operating Supply Current 70 190 µA 0.25 Conversions/Sec Rate Auto-Convert Mode, Averaged Over 4 Seconds 160 290 µA 2 Conversions/Sec Rate Conversion Time 65 115 170 ms From Stop Bit to Conversion Complete (Both Channels) Remote Sensor Source Current D+ Forced to D– + 0.65 V 90 µA High Level 5.5 µA Low Level D– Source Voltage 0.7 V Address Pin Bias Current 50 µA Momentary at Power-On Reset SMBUS INTERFACE Logic Input High Voltage, VIH STBY, SCLK, SDATA 2.2 V VDD = 3 V to 5.5 V Logic Input Low Voltage, VIL STBY, SCLK, SDATA 0.8 V VDD = 3 V to 5.5 V SMBus Output Low Sink Current 6 mA SDATA Forced to 0.6 V ALERT Output Low Sink Current 1 mA ALERT Forced to 0.4 V Logic Input Current, IIH, IIL –1 +1 µA SMBus Input Capacitance, SCLK, SDATA 5 pF SMBus Clock Frequency 0 100 kHz SMBus Clock Low Time, tLOW 4.7 µst LOW Between 10% Points SMBus Clock High Time, tHIGH 4 µst HIGH Between 90% Points SMBus Start Condition Setup Time, tSU:STA 4.7 µs SMBus Repeat Start Condition 250 ns Between 90% and 90% Points Setup Time, tSU:STA SMBus Start Condition Hold Time, tHD:STA 4 µs Time from 10% of SDATA to 90% of SCLK SMBus Stop Condition Setup Time, tSU:STO 4 µs Time from 90% of SCLK to 10% of SDATA SMBus Data Valid to SCLK 250 ns Time from 10% or 90% of Rising Edge Time, tSU:DAT SDATA to 10% of SCLK SMBus Data Hold Time, tHD:DAT 0 µs SMBus Bus Free Time, tBUF 4.7 µs Between Start/Stop Condition SCLK Falling Edge to SDATA Valid Time, tVD,DAT 1 µs Master Clocking in Data NOTES 1Operation at V DD = +5 V guaranteed by design, not production tested. 2Guaranteed by design, not production tested. Specifications subject to change without notice. |
类似零件编号 - ADM1020AR-REEL7 |
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类似说明 - ADM1020AR-REEL7 |
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