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ADG738BRU 数据表(PDF) 4 Page - Analog Devices

部件名 ADG738BRU
功能描述  CMOS, Low-Voltage, 3-Wire Serially-Controlled, Matrix Switches
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADG738BRU 数据表(HTML) 4 Page - Analog Devices

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–4–
REV. 0
ADG738/ADG739
TIMING CHARACTERISTICS
1, 2
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCLK
30
MHz max
SCLK Cycle Frequency
t1
33
ns min
SCLK Cycle Time
t2
13
ns min
SCLK High Time
t3
13
ns min
SCLK Low Time
t4
0
ns min
SYNC to SCLK Active Edge Setup Time
t5
5
ns min
Data Setup Time
t6
4.5
ns min
Data Hold Time
t7
0
ns min
SCLK Falling Edge to
SYNC Rising Edge
t8
33
ns min
Minimum
SYNC High Time
t9
3
20
ns min
SCLK Rising Edge to DOUT Valid
NOTES
1See Figure 1.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of (VIL + VIH)/2.
3C
L = 20 pF, RL = 1 k
Ω.
Specifications subject to change without notice.
SCLK
SYNC
DIN
DB7
DB0
DB7
1
DB0
1
DOUT
NOTE
1DATA FROM LAST WRITE CYCLE
t3
t2
t1
t4
t8
t6
t5
t9
t7
Figure 1. 3-Wire Serial Interface Timing Diagram
(VDD = 2.7 V to 5.5 V. All specifications –40 C to +85 C, unless otherwise noted.)


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